1. Field of the Invention
The present invention generally relates to a nonvolatile memory device used for computer main storage, and more particularly to a nonvolatile memory array that use magnetic memory elements as the individual memory cells.
2. Description of the Related Art
Magnetic random access memory (MRAM or typically referred to as xe2x80x9cMagRamxe2x80x9d) technology is a solid state tunnel junction using magnetic electrodes, and is useful as a storage mechanism. The storage mechanism relies on the relative orientation of the magnetization of two electrodes, and on the ability to discern this orientation by electrical means.
MRAM arrays include an array of magnetic memory cells positioned at the intersections of wordlines and bitlines.
Generally, each cell includes a magnetically changeable or xe2x80x9cfreexe2x80x9d region, and a proximate magnetically reference region, arranged into a magnetic tunnel junction (xe2x80x9cMTJxe2x80x9d) device (e.g., the term xe2x80x9creference regionxe2x80x9d is used broadly herein to denote any type of region which, in cooperation with the free or changeable region, results in a detectable state of the device as a whole).
Generally, the principle underlying storage of data in such cells is the ability to change the relative orientation of the magnetization of the free and reference regions by changing the direction of magnetization along the easy axis (xe2x80x9cEAxe2x80x9d) of the free region, and the ability to thereafter read this relative orientation difference.
More particularly, an MRAM cell is written by reversing the free region magnetization using applied bi-directional electrical currents and resultant magnetic stimuli via its respective bitline and wordline.
The MRAM cell is later read by measuring the resultant tunneling resistance between the bitline and wordline, which assumes one of two values depending on the relative orientation of the magnetization of the free region with respect to the reference region. If the free region is modeled as a simple elemental magnet having a direction of magnetization which is free to rotate but with a strong preference for aligning in either direction along its easy axis (+EA or xe2x88x92EA), and if the reference region is a similar elemental magnet but having a direction of magnetization fixed in the +EA direction, then two states (and therefore the two possible tunneling resistance values) are defined for the cell: aligned (+EA/+EA) and anti-aligned (xe2x88x92EA/+EA).
The resistance of the tunnel junction can assume one of two distinct values with no applied stimulus (e.g., there is a lack of sensitivity of resistance to applied field below the easy axis flipping field strength +/xe2x88x92Hc).
For example, if the applied easy axis field exceeds +/xe2x88x92Hc, then the cell is coerced into its respective high resistance (anti-aligned magnetization of the free region with respect to the reference region) or low resistance (aligned magnetization of the free region with respect to the reference region) state.
Thus, in operation as a memory device, the MRAM device can be read by measuring the tunneling resistance, thereby to infer the magnetization state of the storage layer with respect to the fixed layer. The MRAM can be written by reversing free layer magnetization using external magnetic fields or the magnetic stimuli resulting from bitline and wordline currents. If the free layer is imagined as a simple elemental magnet which is free to rotate but with a strong energetic preference for aligning parallel to the X axis, and if the pinned layer is a similar elemental magnet but frozen in the +X direction, then there are only two states possible for the device (e.g., aligned and not-aligned).
The crosspoint magnetic tunnel junction (MTJ) magneto-resistive memory cell requires a diode (e.g., specifically a diode formed in a thin film of semiconductor material or thin film diode (TFD)) in series with each magnetic tunnel junction (MTJ) memory element. Then, the sense current flows through only one memory element instead of through N elements, as in conventional series architecture magneto-resistive (M-R) memories. This is advantageous in increasing the signal-to-noise ratio (SNR) by a factor of N at the same sense power (or alternatively decreasing the sense power by N squared at an equal SNR.
A key feature of the crosspoint MTJ M-R memory cell is that each memory element is located at the intersection of two metal thin-film wires (TFW), and the memory element electrically contacts both of the TFWs. This design feature makes possible high density very-large-scale-integrated (VLSI) magneto-resistive memory arrays.
The coincidence of write currents in each of the two metal TFWs causes the free magnetic layer of the memory element to switch to a desired state. Switching the free magnetic layer of the selected memory element occurs without changing the state of the memory elements that are in contact with only one of the two TFWs. The write currents change the selected MTJ resistance state, and are on the order of milli-Amperes in both of the two metal TFW conductors. Accordingly, the lower conductor should be physically close to the MTJ for efficiency in generating the required magnetic field to change the MTJ resistance state.
However, a problem is that the MTJ and the lower conductor have not been in close proximity.
Further, since the sensing operation is a resistance measurement, any series resistance or low conductivity switch in series with the sense current path will detract from the signal.
An alternative structure locating the diode coplanar with the silicon substrate has been disclosed in xe2x80x9cMRAM Cell With Remote Diodexe2x80x9d, U.S. patent application Ser. No. 09/116,261, Assignee""s Docket No. AM9-98-025, invented by RE. Scheuerlein, commonly assigned and incorporated herein by reference, which uses metal TFWs having a conventional (square or rectangular) cross-section, and uses a diode formed in the surface of the Si wafer substrate. A vertical connection from the diode up to the lower electrode of the MTJ is located beside the lower metal conductor TEW, which causes the cell area to be larger than a DRAM cell.
However, such a MRAM cell occupies a larger area, and achieves a lower areal density. The uniformity of the electrical characteristics (such as the on resistance) of the switch/diode is required for good memory arrays. The thin film diodes (TFDs) have greater variations due to their manufacturing and inherent materials variations, which reduces the manufacturing yield of arrays of cells using TFD, and therefore increases the cost.
In view of the foregoing and other problems of the conventional systems, it is therefore an object of the present invention to provide a high conductivity diode with high rectification (IF/IR, where IP and IR are respectively the diode forward and reverse bias currents).
Another object of the present invention is to provide a diode which has a minimum total resistance.
Yet another object of the invention is to provides an MRAM cell which occupies a lesser area, and which achieves a higher areal density than the conventional cell mentioned above.
In a first aspect of the invention, a diode is located below the metal TFW, and both the diode and the recessed metal TFW share a non-planar common surface (e.g., also described as a surface with a vertical extent).
With this diode configuration, the MTJ can be in very close proximity to the lower conductor. In the crosspoint MTJ memory cell the diode was formed above the write current conductor, and could only be a thin film diode and thin film diodes have inferior rectification (e.g.,IF/IR) as compared to single crystal Si diodes. In the present invention, the diode is made in a single crystalline semiconductor, as shown in FIG. 1 and as described below. Additionally, in the crosspoint MTJ memory, the diode has been formed above the write conductor, and the MTJ was separated from the conductor by the diode.
The present invention improves upon the MRAM cell with remote diode (which is larger than a DRAM cell) because here the diode location is automatically self-aligned with the recessed metal line, and because the present cell occupies an area of approximately 1 metal pitch by 1 metal pitch. Therefore, high areal density arrays of the present structure are easily fabricated, and the areal density may exceed that of a typical DRAM cell.
In another aspect of the present invention, as shown for example, in FIGS. 2A-2H, a stepwise method is provided to form the above-described structure.
In yet another aspect, a V-groove structure is formed as shown for example in FIGS. 4B-4C.
Hence, the present invention places the MTJ and the lower conductor in close proximity.
In the method of the invention, one set of conductors is buried within the silicon and each intersection point of each buried conductor is surrounded by a layered diode so that electrical connection to the MTJ is from each buried conductor and through the surrounding (e.g., buried) diode.
Further, the buried diode has more uniform electrical characteristics than the TFD.